India Semiconductor Mission 2.0, Exam-Ready Notes

In the last week of September 2025, the committee chaired by the Finance Minister cleared the second phase of the India Semiconductor Mission — one lakh twenty-five thousand crore rupees, announced by the Minister for Electronics and Information Technology, Ashwini Vaishnaw. The number is sixty-four per cent larger than the seventy-six thousand crore of the first phase approved in December 2021. The scope is larger too: not just fabrication plants and design, but memory and display manufacturing, research and development, talent pipelines, and — for the first time — support for making the equipment that makes chips.

This card, dated as the clearance made headlines, assembles the exam kit: the new numbers and what they buy, the first-phase scorecard that justifies phase two, the ecosystem logic — design, fabs, ATMP, equipment — in one diagram of the mind, the geopolitics that made semiconductor self-reliance a G20 vocabulary word, and the talent-and-R&D pillars that decide whether the money converts into capability. It is the industrial-policy sequel to this series’ earlier Viksit Bharat growth card, and it links there directly.

The Numbers and the Scope

What phase two actually buys.

1. The headline. One lakh twenty-five thousand crore rupees for ISM 2.0, cleared by the ministerial committee in September 2025 — a sixty-four per cent step-up from phase one’s seventy-six thousand crore of December 2021.
2. The widened scope. Explicit coverage of memory and display manufacturing alongside logic fabs, design-linked incentives, research and development, and talent programmes — phase one’s fab-plus-design frame widened to the full stack.
3. The equipment opening. For the first time, incentives extend to semiconductor equipment manufacturing — the tool-makers whose absence kept earlier industrial-policy rounds dependent on imports.
4. The skin-in-the-game principle. Ministerial briefings stressed industry co-investment: government money catalyses but does not substitute private capital, and applicant commitments are binding.
5. The exam line. One-twenty-five versus seventy-six, full-stack scope, first-time equipment incentives, binding co-investment — the four-clause summary.

The Phase-One Scorecard

Why phase two could be sold politically.

1. The fabs. Phase one seeded the Dholera and Sanand fabs — the Tata-PSMC and Micron-backed projects — plus the CG Power OSAT facility: India’s first working silicon lineage after decades of false starts.
2. The ATMP layer. Micron’s Sanand assembly-and-test plant broke ground and moved toward production timelines — the packaging end of the value chain where India’s first jobs and exports actually materialise.
3. The design wins. Around a dozen design-linked incentives supported start-ups from Bengaluru to Noida building IPs on global processes — the quiet layer where Indian engineering already had comparative advantage.
4. The 100-day context. The September clearance landed in the new government’s first hundred days — industrial policy as early-tenure signal, a political-economy point mains answers can deploy.
5. The exam line. Two fabs plus ATMP plus design wins, delivered inside three years — the scorecard that unlocked the bigger cheque.

The Ecosystem Logic

The five layers in one mental diagram.

1. Design. Indian engineers already design significant global silicon; design-linked incentives convert service capability into IP ownership — the highest value-per-rupee layer.
2. Fabrication. The capital-guzzling layer: fabs turn designs into silicon; Dholera and Sanand are the anchors around which suppliers cluster.
3. ATMP. Assembly, testing, marking and packaging — labour-intensive, sooner to employment, the layer where phase one’s first output actually flowed.
4. Equipment. The newly opened layer: making the tools and sub-systems, where Germany, Japan and the US dominate and where import-dependence otherwise stays structural.
5. Talent and R&D. The layer that makes the rest durable: curriculum upgrades, the two-lakh-talent-vision under the mission’s human-resource programmes, and R&D anchors at C-DAC and the IITs.
6. The exam line. Design, fab, ATMP, equipment, talent-and-R&D — name the five layers and attach one Indian example to each.

The Geopolitical Weight

Why chips became strategy.

1. The concentration problem. Leading-edge fabrication sits in Taiwan and Korea, equipment in the US, Japan and Europe, memory in Korea — a concentration the pandemic and the export-control era turned into national-security arithmetic.
2. The China factor. Export controls and the subsidy race — the US CHIPS Act, Europe’s Chips Act, Japan’s Renaissance programme — moved industrial policy from taboo to mainstream, the frame in which ISM was conceived and ISM 2.0 is funded.
3. The trusted-supply-chain pitch. India offers a democratic, English-speaking, engineering-deep alternative node — the China-plus-one logic applied to the most strategic input of all.
4. The diplomatic dividend. Semiconductor cooperation now anchors the iCET and TRUST frameworks with the United States and technology tracks in the Quad — chips as bridge-building currency.
5. The exam line. Concentration risk, subsidy-race context, trusted-node pitch, iCET-TRUST diplomacy — the geopolitics quartet.

Talent, R&D and the Conversion Challenge

Where missions succeed or quietly fail.

1. The talent vision. The mission’s human-resource programmes aim to prepare on the order of two lakh engineers for the semiconductor value chain — curriculum revision, fab-ready MTech tracks and faculty development together.
2. The R&D anchors. C-DAC programmes, IIT research centres and the mission’s R&D component fund pre-commercial work — the layer that keeps the ecosystem from being assembly-only.
3. The conversion risk. Global semiconductoring is a decade game: fabs slip, demand cycles bite, and subsidy races can outrun demand — the exam-honest caveat every evaluation answer should carry.
4. The federal link. States compete with land, power and water packages — Gujarat’s Dholera and Assam’s package for the CG-OSAT show the mission riding on state-level execution, a GS2 angle.
5. The exam line. Two-lakh talent target, C-DAC-IIT anchors, decade-long horizon, state-skin-in-the-game — the conversion four.

How Exams Ask This Card

Question shapes and their marking engines.

1. Number pairs. One-twenty-five versus seventy-six — the sixty-four per cent step-up is the stat prelims will test as a pair, not a single number.
2. Industrial-policy evaluation. Critically examine ISM 2.0 as industrial policy — the twenty-marker this card drafts: numbers-and-scope, scorecard, ecosystem layers, conversion challenge as the four paragraphs.
3. Geopolitics framing. Semiconductors and strategic autonomy — the answer that must deploy the concentration map and the China-plus-one pitch with the iCET-TRUST layer.
4. Federal dimension. States in semiconductor industrial policy — the GS2 crossover where Gujarat and Assam examples earn the extra mark.
5. Integration question. Link this card to the Viksit Bharat 2047 growth story — completing the tie to the earlier card in this series, which this post links to directly.

Quick Revision: Ten Lines

One glance before the hall.

1. The clearance. September 2025: ministerial finance-panel cleared one lakh twenty-five thousand crore rupees for ISM 2.0.
2. The step-up. Sixty-four per cent over phase one’s seventy-six thousand crore, approved December 2021.
3. The scope. Memory and display manufacturing, design incentives, R&D and talent joins fabs in phase two.
4. The first. Semiconductor equipment manufacturing incentives — the first time the tool-makers’ layer is funded.
5. The principle. Industry co-investment with binding commitments — government catalyses, does not substitute.
6. The scorecard. Dholera and Sanand fabs, Micron ATMP, CG Power OSAT and design-linked wins justified phase two.
7. The layers. Design, fabrication, ATMP, equipment, talent-and-R&D — the five-layer ecosystem diagram.
8. The geopolitics. Taiwan-Korea concentration, export controls, subsidy race, trusted-supply-chain pitch.
9. The conversion. Two-lakh talent target, C-DAC-IIT anchors, decade horizon, state-level execution.
10. The exam angle. Step-up statistic, five layers with examples, honest conversion caveat — the three habits that score.

Conclusion: From Policy to Silicon

ISM 2.0’s lakh-and-a-quarter crore is best read as recognition and wager at once: recognition that phase one actually delivered fabs, packaging plants and design wins inside three years, and a wager that the next layer — memory, display, equipment, deeper R&D — can be bought with scale and discipline. The mission’s exam significance is precisely this double character: evidence that targeted industrial policy can move in India, evidence also that chips punish impatience more than any other industry. Hook the number pair, draw the five layers, name the geopolitical frame, and carry the conversion caveat — that is the full kit. This is the industrial-policy chapter of this series’ Viksit Bharat arc; the growth-story card it links to below carries the macro frame, and the semiconductors here are the pick-and-shovel end of the same ambition.